Design Automation Engineer

Job Description

This position is for a technical contributor (individual) role in the domain of back-end for automating device templates using virtuoso SKILL, and sign-off for TI using ICV/Calibre flows in the Technology Development, RnD team of Intel. In this position, you will be expected to deploy tools/flows methodologies for device/p-cell development, Tape-in, and review post silicon results. You will be working with the research team for device/p-cell development and implementing floor-plan, placement, routing, extraction, and tape-in of various designs. You will be working on integration methodologies of nominal, HV, and EHV voltage device templates into IPs. Develop and support python based flows, and set up the same for performing regressions on the specified tools as per design flow. You will be expected to provide necessary data in making decisions on tools and methodologies of choice in the associated domains on leading-edge process nodes. This role also gives the opportunity to work on the newest technology, with key stakeholders in the design, central CAD, and other projects on similar technologies to enable next-generation tools and methodologies in process, extraction, and domains by closely working with both external and internal vendors. You may need to respond to users in the design team 's requests or events as they occur, and develops solutions to problems utilizing formal education and engineering judgment.

Qualifications

Candidate needs to have Master 's degree (M.Tech/MS) in Electronics Engineering or equivalent qualification from reputed institute with 2-year experience in Cadence virtuoso SKILL, python, TCL, layout development. He should have good knowledge of VLSI and basic electronics. Understanding fabrication and process technology will be added advantage. Any knowledge/experience on C/C with data structures and programming would be a plus point.